1. Field of the Invention
The present invention relates to processors and computing devices. More specifically the present invention relates to a multiple function floating point arithmetic execution unit in a processor.
2. Description of the Related Art
Very Long Instruction Word (VLIW) processor architectures achieve efficient performance by exploiting instruction level parallelism in which a compiler performs most instruction scheduling and parallel dispatching at compile-time, reducing the operating burden at run-time. By moving scheduling tasks to the compiler, a VLIW processor avoids both the operating latency and the large and complex circuitry associated with on-chip instruction scheduling logic.
Each VLIW instruction includes multiple independent operations for execution by the processor in a single cycle. A VLIW compiler forms these instructions according to precise conformance to the structure of the processor, including the number and type of execution units, as well as execution unit timing and latencies. The compiler groups the operations into a wide instruction for execution in one cycle. At run-time, the wide instruction is applied to the various execution units with little decoding. Execution units which are idle in a particular cycle are issued a no-operation (NOP) signal.
The execution units in a VLIW processor typically include arithmetic units such as floating point arithmetic units. One example of a VLIW processor that includes floating point execution units is described by R. K. Montoye, et al. in "Design of the IBM RISC System/6000 floating point execution unit", IBM J.Res.Develop., V. 34, No. 1, pp. 61-62, January 1990. The Montoye system floating point unit is a multiply-add fused (MAF) dataflow processor unit. The MAF unit performs a double-precision multiply operation in a single cycle and a double-precision add operation in the following cycle. The MAF architecture supports the exploitation of the multiply-add capability through a set of "multiply-add" instructions.
A second example of a VLIW processor including a floating point execution unit is described by Hicks, T. N. et al, in "POWER2 Floating-Point Unit: Architecture and Implementation", PowerPC and POWER2: Technical Aspects of the new IBM RISC System/6000, IBM Corporation, SA23--2737, pp.45-54, 1994. The Power2 floating point unit achieves a megaflop execution rate by integrating dual generic MAF ALUs, doubling the instruction bandwidth and quadrupling the data bandwidth over the POWER FPU bandwidth. The Power2 floating point unit includes support for additional functions using dynamic instruction scheduling techniques.
What is needed is a VLIW arithmetic processor which further improves floating point performance.